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| IMAGE SENSOR CCD area image sensor S7170-0909, S7171-0909 512 x 512 pixels, Back-thinned FFT-CCD Hamamatsu developed Multi Pin-Phase (MPP) mode back-thinned FFT- CCDs S7170-0909, S7171-0909 specifically designed for low-light-level detection in scientific applications. S7170-0909, S7171-0909 have sensitivity from the UV to near-IR as well as having low dark current and wide dynamic range. Stability of the spectral response curve is also achieved for high precision measurements. Either one-stage or two-stage thermoelectric cooler is built into the package (S7171-0909, S7172-0909). At room temperature operation, the device can be cooled down to -10 C by one-stage cooler and -30 C by two-stage cooler, respectively. In addition since both the CCD chip and the thermoelectric cooler are hermetically sealed, no dry air is required, thus allowing easy handling. Features Applications l 512 x 512 pixel format l Greater than 90 % quantum efficiency at peak sensitivity wavelength l Wide spectrum range l Low readout noise l Wide dynamic range l MPP operation l Non-cooled types: S7170-0909 l Scientific measuring instrument l Semiconductor inspection l UV imaging l Bio-photon observation One-stage TE-cooled types: S7171-0909 s Selection guide Type No. S7170-0909 S7171-0909 Cooling Non-cooled One-stage TE-cooled Number of total pixels 532 x 520 532 x 520 Number of active pixels 512 x 512 512 x 512 Active area [mm (H) x mm (V)] 12.288 x 12.288 12.288 x 12.288 Note) Two-stage TE-cooled type (S7172-0909) is also available. s General ratings Parameter Pixel size Number of active pixels Vertical clock phase Horizontal clock phase Output circuit Package Built-in cooler Window *1: Window-less is available upon request. S7170-0909 S7171-0909 24 (H) x 24 (V) m 512 (H) x 512 (V) 2 phase 2 phase One-stage MOSFET source follower 24 pin ceramic DIP (refer to dimensional outlines) One-stage Sapphire glass *1 1 CCD area image sensor s Absolute maximum ratings (Ta=25 C) Parameter Operating temperature Storage temperature OD voltage RD voltage ISV voltage ISH voltage IGV voltage IGH voltage SG voltage OG voltage RG voltage TG voltage Vertical clock voltage Horizontal clock voltage Symbol Topr Tstg VOD VRD VISV VISH VIG1V, VIG2V VIG1H, VIG2H VSG VOG VRG VTG VP1V, VP2V VP1H, VP2H S7170-0909, S7171-0909 Min. -50 -50 -0.5 -0.5 -0.5 -0.5 -10 -10 -10 -10 -10 -10 -10 -10 Typ. Max. +30 +70 +25 +18 +18 +18 +15 +15 +15 +15 +15 +15 +15 +15 Unit C C V V V V V V V V V V V V s Operating conditions (MPP mode, Ta=25 C) Parameter Output transistor drain voltage Reset drain voltage Output gate voltage Substrate voltage Test point (vertical input source) Test point (horizontal input source) Test point (vertical input gate) Test point (horizontal input gate) High Vertical shift register clock voltage Low High Horizontal shift register clock voltage Low High Summing gate voltage Low High Reset gate voltage Low High Transfer gate voltage Low Symbol VOD VRD VOG VSS VISV VISH VIG1V, VIG2V VIG1H, VIG2H VP1VH, VP2VH VP1VL, VP2VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSGL VRGH VRGL VTGH VTGL Min. 18 11.5 1 -8 -8 4 -9 4 -9 4 -9 4 -9 4 -9 Typ. 20 12 3 0 VRD VRD 0 0 6 -8 6 -8 6 -8 6 -8 6 -8 Max. 22 12.5 5 8 -7 8 -7 8 -7 8 -7 8 -7 Unit V V V V V V V V V V V V V s Electrical characteristics (Ta=25 C) Parameter Symbol Min. Typ. Signal output frequency fc Vertical shift register capacitance CP1V, CP2V 6,400 Horizontal shift register capacitance CP1H, CP2H 120 Summing gate capacitance CSG 7 Reset gate capacitance CRG 7 Transfer gate capacitance CTG 150 Charge transfer efficiency *2 CTE 0.99995 0.99999 DC output level *3 Vout 12 15 Output impedance *3 Zo 3 Power consumption *3 *4 P 15 *2: Charge transfer efficiency per pixel, measured at half of the full well capacity. *3: The values depend on the load resistance. (Typical, VOD=20 V, Load resistance=22 k) *4: Power consumption of the on-chip amplifier. Max. 1 18 Unit MHz pF pF pF pF pF V k mW 2 CCD area image sensor S7170-0909, S7171-0909 Max. 12,000 600 16 10 Unit V e - s Electrical and optical characteristics (Ta=25 C, unless otherwise noted) Parameter Symbol Min. Typ. Saturation output voltage Vsat Fw x Sv Vertical 150,000 300,000 Full well Fw capacity Horizontal 300,000 600,000 CCD node sensitivity Sv 1.8 2.2 Dark current *5 25 C 4,000 DS 0 C 200 (MPP mode) Readout noise *6 Nr 8 Line binning 18,750 75,000 7 Dynamic range * DR Area scanning 9,375 37,500 8 Photo response non-uniformity * PRNU 3 Spectral response range 200 to 1100 *5: Dark current nearly doubles for every 5 to7 C increase in temperature. *6: Operating frequency is 150 kHz. *7: Dynamic Range (DR) = Full well/Readout noise *8: Measured at half of the full well capacity. Fixed pattern noise (peak to peak) Photo Response Non-Uniformity (PRNU) [%] = x 100 Signal V/e e /pixel/s e rms % nm - s Spectral response (without window) *9 100 90 (Typ. Ta=25 C) BACK-THINNED s Spectral transmittance characteristic of window material 100 90 80 (Typ. Ta=25 C) QUANTUM EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 200 400 600 800 1000 1200 FRONT-SIDED (UV COAT) FRONT-SIDED TRANSMITTANCE (%) 70 60 50 40 30 20 10 0 100 200 300 400 500 600 700 800 900 1000 WAVELENGTH (nm) KMPDB0058EA WAVELENGTH (nm) KMPDB0102EA *9: Spectral response with sapphire window is decreased by the transmittance q Window material Type No. S7170-0909 S7171-0909 S7172-0909 (two-stage TEcooled type) *10: Hermetic sealing Window material Sapphire glass *10 (option: window-less) 3 CCD area image sensor s Dark current vs. temperature 10000 (Typ.) S7170-0909, S7171-0909 DARK CURRENT (e-/pixel/s) 1000 100 10 1 0.1 -50 -40 -30 -20 -10 0 10 20 30 TEMPERATURE (C) KMPDB0037EB s Device structure (Conceptual drawing of top view) THINNING 22 23 21 20 15 14 13 4 BEVEL THINNING V 24 1 5 4 3 2 12345 H 12 11 2 3 4 5 8 9 10 V=512 H=512 4 BLANK 512 SIGNAL OUT 4 BLANK 8 BEVEL 4 BEVEL KMPDC0075EA 4 4 BEVEL 512 SIGNAL OUT CCD area image sensor s Timing chart S7170-0909, S7171-0909 Area scanning 1 (low dark current mode) INTEGRATION PERIOD (Shutter must be open) Tpwv 1 P1V P2V, TG P1H P2H, SG RG OS Tovr P2V, TG P1H Tpwh, Tpws ENLARGED VIEW 2 3 READOUT PERIOD (Shutter must be closed) 4..519 520512 + 8 (BEVEL) P2H, SG RG OS Tpwr D1 D2 D3 D4 D18 D5..D12, S1..S512, D13..D17 D19 D20 KMPDC0119EA Parameter Symbol Pulse width Tpwv P1V, P2V, TG Rise and fall time Tprv, Tpfv Pulse width Tpwh P1H, P2H Rise and fall time Tprh, pfh Duty ratio Pulse width Tpws SG Rise and fall time Tprs, Tpfs Duty ratio Pulse width Tpwr RG Rise and fall time Tprr, Tpfr TG - P1H Overlap time Tovr *11: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. Remark *11 *11 - Min. 6 200 500 10 500 10 100 5 3 Typ. 50 50 - Max. - Unit s ns ns ns % ns ns % ns ns s 5 CCD area image sensor S7170-0909, S7171-0909 Area scanning 2 (large full well mode) INTEGRATION PERIOD (Shutter must be open) Tpwv 1 P1V P2V, TG P1H P2H, SG RG OS Tovr P2V, TG P1H Tpwh, Tpws ENLARGED VIEW 2 3 READOUT PERIOD (Shutter must be closed) 4..519 520512 + 8 (BEVEL) P2H, SG RG OS Tpwr D1 D2 D3 D4 D18 D5..D12, S1..S512, D13..D17 D19 D20 KMPDC0120EA Parameter Symbol Remark Pulse width Tpwv *12 P1V, P2V, TG Rise and fall time Tprv, Tpfv Pulse width Tpwh *12 P1H, P2H Rise and fall time Tprh, Tpfh Duty ratio Pulse width Tpws SG Rise and fall time Tprs, Tpfs Duty ratio Pulse width Tpwr RG Rise and fall time Tprr, Tpfr TG - P1H Overlap time Tovr *12: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. Min. 6 200 500 10 500 10 100 5 3 Typ. 50 50 - Max. - Unit s ns ns ns % ns ns % ns ns s 6 CCD area image sensor s Dimensional outlines (unit: mm) S7170-0909 WINDOW 14.8 ACTIVE AREA 12.288 S7170-0909, S7171-0909 12.288 12.8 22.4 2.54 34.0 1st PIN INDICATION PAD PHOTOSENSITIVE SURFACE 3.4 4.0 4.8 3.0 2.4 (24 x) 0.5 KMPDA0084EA S7171-0909 WINDOW 14.8 ACTIVE AREA 12.288 12.288 12.8 22.9 22.4 6.9 2.54 34.0 42.0 50.0 1st PIN INDICATION PAD PHOTOSENSITIVE SURFACE 6.3 7.7 KMPDA0085EB TE-COOLER 3.0 1.0 (24 x) 0.5 4.8 4.0 19.0 22.9 7 CCD area image sensor s Pin connections S7170-0909, S7171-0909 S7170-0909 S7171-0909 Remark Pin (standard operation) No. Symbol Function Symbol Function 1 RD Reset drain RD Reset drain +12 V 2 OS Output transistor source OS Output transistor source RL=10 k to 100 k 3 OD Output transistor drain OD Output transistor drain +20 V 4 OG Output gate OG Output gate +3 V 5 SG Summing gate SG Summing gate Same pulse as P2H 6 7 8 P2H CCD horizontal register clock-2 P2H CCD horizontal register clock-2 9 P1H CCD horizontal register clock-1 P1H CCD horizontal register clock-1 10 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2) 0V 11 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1) 0V 12 ISH Test point (horizontal input source) ISH Test point (horizontal input source) Connect to RD TG *13 TG *13 13 Transfer gate Transfer gate Same pulse as P2V 14 P2V CCD vertical register clock-2 P2V CCD vertical register clock-2 15 P1V CCD vertical register clock-1 P1V CCD vertical register clock-1 16 Th1 Thermistor 17 Th2 Thermistor 18 PTE-cooler19 P+ TE-cooler+ 20 SS Substrate (GND) SS Substrate (GND) GND 21 ISV Test point (vertical input source) ISV Test point (vertical input source) Connect to RD 22 IG2V Test point (vertical input gate-2) IG2V Test point (vertical input gate-2) 0V 23 IG1V Test point (vertical input gate-1) IG1V Test point (vertical input gate-1) 0V 24 RG Reset gate RG Reset gate *13: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as P2V. s Specifications of built-in TE-cooler (S7171-0909) Parameter Symbol Condition Typ. Unit Internal resistance Rint Ta=25 C 2.1 Maximum current *14 Imax Tc *15=Th *16=25 C 2.0 A Maximum voltage Vmax Tc *15=Th *16=25 C 4.2 V Maximum heat absorption *17 Qmax 4.5 W Maximum temperature of heat radiating side 70 C *14: Maximum current Imax: If the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60 % of this maximum current. *15: Temperature of the cooling side of thermoelectric cooler. *16: Temperature of the heat radiating side of thermoelectric cooler. *17: Maximum heat absorption Qmax. This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit. 6 (Typ. Ta=25 C) VOLTAGE vs. CURRENT CCD TEMPERATURE vs. CURRENT 5 20 30 VOLTAGE (V) 4 10 3 0 2 -10 1 -20 0 0 0.5 1.0 1.5 -30 2.0 CURRENT (A) KMPDB0180EA 8 CCD TEMPERATURE (C) CCD area image sensor s Specifications of built-in temperature sensor (S7171-0909) S7170-0909, S7171-0909 A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and absolute temperature is expressed by the following equation. R1 = R2 x expB (1 / T1 - 1 / T2) where R1 is the resistance at absolute temperature T1 (K) R2 is the resistance at absolute temperature T2 (K) B is so-called the B constant (K) The characteristics of the thermistor used are as follows. R (298K) = 10 k B (298K / 323K) = 3450 K 1 M (Typ. Ta=25 C) RESISTANCE 100 k 10 k 220 240 260 280 300 TEMPERATURE (K) KMPDB0111EA s Precaution for use (Electrostatic countermeasures) q Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. q Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. q Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. q Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. s Element cooling/heating temperature incline rate Element cooling/heating temperature incline rate should be set at less than 5 K/min. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. (c)2006 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvagen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1028E06 Feb. 2006 DN 9 |
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